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Preliminary
The suitable memory available in the MC68HC12B32 system is 32 kbs of read-only memory (ROM). The ROM array is arranged in a 16-bit configuration and may read as bytes, aligned words or uneven words. A bus cycle represents access time for byte and aligned word access whereas, for uneven words, two-word cycles are implemented.
Before using the Analog to Digital (ATD) converter, it must be powered up. When a conversion is initialized, The ADT capacitor is charged with the input signal voltage and subsequently held constant for the duration of AD conversion; thus, the input pins charges the capacitor.
The MC68HC12B32 ATD consists of eight basic conversion modes, which are selected by using the ATD control register 5. In the non- scan approach, the SCF bit is set once the series of four or eight changes have been made, and the ATD subsystem stops. In the scan modes, the setting of SCF is like the non-scan mode but ATD loops the sequence. However, both modes set the CCF bit associated with each register when that register is supplied with the required conversion result. After reading the result, the flag is cleared and the conversions are initialized by writing to the control registers (Freescale Semiconductor, Inc. 301).
During the conversion operation, there are several ATD mode operations available with the MC68HC12B32 ATD. These modes include: 1. Stop it causes all clocks to halt, hence aborting any conversion cycle in progress. 2. Wait ATD translation proceeds unless the AWAI bit in ATDCTL2 register is set. 3. BDN debug decisions obtainable as set in register ATDCTL3. 4. User ATD carries on unless ADPU is cleared. 5. ADPU ATD operations are halted if ADPU = 0, but registers can be obtained (Freescale Semiconductor, Inc. 312).
For the ATD to read channel 0, the MULT bit must be set to 0 so as to enable a single-channel operation. Then channel 0 is selected by using the channel select bits, CC, CB and CA which are set to 0. Concerning the status of ATD, the ATD status register is used to monitor the conversion status. The register contains the flags signifying the end of ATD conversions; the Sequence Conversion Flag (SCF) is set at the end of the translation sequence while the Conversion Complete Flag (CCF) is set at the end of conversion for a specific channel.
The default period for the COP is 218 or 213 of the bus rate clocks. The COP timer bit (COPT) in the System Options Register (SOPT) can be used to select one of the default modes (Freescale Semiconductor 2).
The RTI is enabled by setting the Real-Time Interrupt Enable Bit (RTIE) to 1, which is found in the RTICL. Therefore, the pseudo-interrupt vector location for a RTI in the 6212 EVB is $FFFD, $FFF1.
Program Analysis and Design
The program below is a C program that performs A/D conversion using the ATD sub-module. It repetitively activates the ATD four times and calculates the standard reading of conversion. The comments included therein documents the functioning of the code.
ATD Program in C
#include /* include derivative */
/* define the value for ATDCTL2
*Power up ATD */
#define ATDCTL2_VAL 0x80;
/* define the value for ATDCTL3
* 4 conversion per cycle S8C:S1C = 0100*/
#define ATDCTL3_VAL 0x20
/*define the value for ATDCTL4
* 8-bit resolution SRES8 = 1
* A/D conversion clock periods = 16 SMP1:SMP0 = 11
* Set prescaler to divide by 8 PRS4:PRS0 = 00011 */
#define ATDCTL4_VAL 0xE3
/*define the AD mode for ATDCTL5
* DJM = 1 Right Justified Data
* DSGN = 0 Unsigned Data
* SCAN = 0 Single conversion
* MULT = 0 1 conversion on a single channel
* CC, CB, CA = 001 Analog channel 1 */
#define ATDCTL5_VAL 0x81
void main(void) {
char c;
volatile unsigned int atd_val;
/* Initialize Input/Output */
/* Power up the ATD and invoke ATDCTL2 */
ATDCTL2 = ATDCTL2_VAL;
/* Generate a delay > 60 usec */
for ( c = 0; c < 60; ++c );
/* Initialize ATDCTL3 */
ATDCTL3 = ATDCTL3_VAL;
/* Initialize ATDCTL4 */
ATDCTL4 = ATDCTL4_VAL;
/* Enable the PORTA */
DDRT_DDRT1 = 1;
PTT_PTT1 = 1;
/* Loop */
for(;;) {
/* Start the translation by noting the scan select information
* to ATDCTL5 */
ATDCTL5 = ATDCTL5_VAL;
/* Wait for the conversion to be end */
while (ATDSTAT0_SCF == 0);
atd_value = (ATDDR0L + ATDDR1L + ATDDR2L + ATDDR3L)/4;
} /* wait ceaselessly */
Works Cited
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Freescale Semiconductor, Inc. M68HC12 Microcontrollers . Motorola Semiconductors. 9.6. (2004). 69 71.
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Freescale Semiconductor. Computer Operating Properly (COP) Watchdog. 2008.
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